Dr. Rajendra Bahadur Singh


Assistant Professor (On Contract)

Other
University School Of Information And Communication Technology
M.Tech (VLSI Design)
Linear IC Applications, Digital Logic Design, CMOS VLSI Design


Professional
Updates


Books



Patents



Journals

  • Rajendra Bahadur Singh, Anurag Singh Baghel, “Simulated Annealing algorithm for VLSI floorplanning for soft blocks”, International Journal of Computer Science and Information Security, April 2018.
  • Kumar Abhinav Rajput, Rajendra Bhadur Singh, “Reduce Leakage Power of SRAM Cell using Variable Body Biasing and Force Sleep Technique in Submicron Technology”, International Journal of Computer Networks and Wireless Communications (IJCNWC), ISSN: 2250-3501 Vol.6, No 3, May-June 2016.
  •  Akash Kumar, Rajendra Bhadur Singh, “Asymmetric 6T SRAM cells using a boosted bit line write assist technique”, International Journal of Computer Science and Information Technology & Security (IJCSITS), ISSN: 2249-9555 Vol.6, No3, May-June 2016.
  • Kumari Pritee, Rajendra Bhadur Singh, “5-bit Folded Interpolated ADC in 90-nm CMOS Technology”, International Journal of Computer Networks and Wireless Communications (IJCNWC), ISSN: 2250-3501 Vol.6, No 3, May-June 2016.
  • Sanjay Kumar Chauhan, Rajesh Mishra, Rajendra Bhadur Singh, “Estimation of Software Reliability on the Basis of Bits for Embedded System”, International Journal of Engineering Research and General Science Volume 4, Issue 2, March-April, 2016 ISSN 2091-2730.
  • Prateek Khurana, Rajat Arora, Monika Nagaria, Megha Sharma, Rajendra Bhadur Singh, “FPGA-Based Interfacing For 8-Bit and 32-Bit Electronic Devices”, IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163, ISSN: 2321-7308, Volume: 03 Issue: 05, May-2014.


Conference Proceedings

  • Ayush Agarwal, Rajendra Bahadur Singh, “Comparative Analysis of Traveling Salesman Problem using Metaheuristic Algorithms, Proceedings of International Conference on Communication and Computing Systems By Taylor 849-853, 2017.
  • Rajendra Bahadur Singh, Anurag Singh Baghel, Ayush Agarwal, “A review on VLSI floorplanning optimization using metaheuristic algorithms”, 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai.
  •  Neeraj Kumar Niranjan, Rajendra Bahadur Singh, Navaid Z. Rizvi, “Parametric Analysis of a hybrid 1-bit full adder in UDSM and CNTFET technology”, International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai 2016.